A Systolic VLSI Architecture for Complex SVD

This thesis presents a systolic algorithm for the SVD of arbitrary complex matrices, based on the cyclic Jacobi method with \parallel ordering". As a basic step in the algorithm, a two-step, two-sided unitary transformation scheme is employed to diagonalize a complex 2 2 matrix. The transformations are tailored to the use of CORDIC (COordinate Rotation Digital Computer) algorithms for high speed arithmetic. The complex SVD array is modeled on the Brent-Luk-VanLoan array for real SVD. An array with O(n) processors is required to compute the SVD of a n n matrix in O(n logn) time. An architecture for the complex 2 2 processor with an area complexity twice that of a real 2 2 processor, is shown to have the best area/time tradeo for VLSI implementation. Despite the involved nature of computations on complex data, the computation time for the complex SVD array is less than three times that for a real SVD array with a similar CORDIC based implementation.